期刊論文
[J5]

Yi-Ming Wang and Shih-Nung Wei, “Low-Power Fast-Lock Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit,” International Journal of Electrical Engineering, vol. 19, pp. 85-94, 2012. (IJEE) (EI)
[J4]

Chung-Hsun Huang*, Tzung-Lin Wu, and Yi-Ming Wang, “Adaptive Pseudo Dual Keeper for Wide Fan-In Dynamic Circuits,” IEEE Trans. On Circuits and Systems II, vol. 58, pp. 672-676, Oct. 2011. (TCAS-II) (SCI, EI)
[J3] Chung-Hsun Huang*, Tzung-Lin Wu, and Yi-Ming Wang, “High-Performance Strength Adaptive Keeper for High Noise-Tolerant Wide Fan-In Dynamic Circuits Circuits,” International Journal of Electrical Engineering,  vol. 18, pp. 107-113, 2011. (IJEE) (EI)
[J2]

Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, and Yi-Ming Wang, “A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 45, pp. 1036-1047, May 2010. (JSSC) (SCI, EI)
[J1]

Yi-Ming Wang and Jinn-Shyan Wang, “A low-power half-delay-line fast skew-compensation circuit,” IEEE J. Solid-State Circuits, vol. 39, pp. 906-918, June 2004. (JSSC) (SCI, EI)
　 　
會議論文
[C14] Shih-Nung Wei, Yi-Ming Wang and Jyun-Hua Peng, “An Output Tracking Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit,” in Proc. IEEE International Symposium on Circuits and Systems, May 2012, pp. 1648-1651. (ISCAS)(EI)
[C13] Yi-Ming Wang, Jen-Tsung Yu, Yuandi Surya, and Chung-Hsun Huang, “A Compact Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit,” in Proc. IEEE International SOC Conference, Sep 2011, pp. 42-47. (SOCC) (EI)
[C12] Chun-Yuan Cheng, Jinn-Shyan Wang, Yung-Chen Chien, and Yi-Ming Wang,  “A 2-locking-cycle skew-compensation circuit with the capability of tracking runtime-variations,” in Proc. IEEE International Symposium on Solid-State and Integrated Circuit Technology, Nov 2010, pp. 176-179. (ICSICT) (EI)
[C11] Chung-Hsun Huang and Tzung-Lin Wu, and Yi-Ming Wang, “Strength Adaptive Keeper for High-Performance and High Noise-Immunity Wide Fan-In Dynamic Circuits,” in Proc. 21th VLSI Design/CAD Symposium, Aug 2010, pp. 131-134.
[C10] Jinn-Shyan Wang , Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, and Yi-Ming Wang, "A 55nm 1GHz One-Cycle-Locking De-Skewing Circuit," in Proc. IEEE International Symposium on Circuits and Systems, May 2010, pp. 1755-1758. (ISCAS)(EI)
[C9] Chung-Hsun Huang, Tzung-Lin Wu1 and Yi-Ming Wang, “Compact Precharging-Transistor-Less Dynamic Circuits For High Noise-Immunity Applications,” in Proc. IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test, pp. 266-269, April 2010. (VLSI-DAT)(EI)
[C8] Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, and Yi-Ming Wang, “A 0.67μW/MHz, 5ps Jitter, 4 Locking Cycles, 65nm ADDLL,” in Proc. IEEE Asian Solid-State Circuits Conference, Nov. 2007, pp. 300-303. (ASSCC)(EI)
[C7] Jinn-Shyan Wang , Jian-Shiun Chen, Yi-Ming Wang and Chingwei Yeh, “A 230-to-500mV 375kHz-to-16MHz 32b RISC Core in 0.18um CMOS,” in ISSCC Digest of Technical Papers, Feb. 2007, pp. 294-295. (ISSCC)(EI)
[C6] Jinn-Shyan Wang, Yi-Ming Wang, Chun-Yuan Cheng, and Yu-Chia Liu, “An Improved SAR Controller for DLL Applications,” in Proc. IEEE International Symposium on Circuits and Systems, May 2006, pp. 3898-3901. (ISCAS)(EI)
[C5] Yi-Ming Wang, Chang-Fen Hu, and Yi-Jen Chen, and Jinn-Shyan Wang, “An all-digital pulsewidth control loop,” in Proc. IEEE International Symposium on Circuits and Systems, May 2005, pp. 1258-1261. (ISCAS)(EI)
[C4] Jinn-Shyan Wang, Yi-Ming Wang, Chi-Haw Chen, and Yu-Chia Liu, “An ultra low power, fast lock-in, small jitter, all digital delay locked loop,” in ISSCC Digest of Technical Papers, Feb. 2005, pp. 422-423. (ISSCC)(EI)
[C3] Yi-Ming Wang and Jinn-Shyan Wang, “An all-digital 50% duty-cycle corrector,” in Proc. IEEE International Symposium on Circuits and Systems, May 2004, vol. 2, pp. 925-928. (ISCAS)(EI)
[C2] Yi-Ming Wang and Jinn-Shyan Wang, “A reliable low-power fast skew-compensation circuit,” in Proc. Asia and South Pacific Design Automation Conference, Jan. 2004, pp. 547-548. (ASP-DAC)(EI)
[C1] Po-Hui Yang, Jinn-Shyan Wang and Yi-Ming Wang, “A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops” in Proc. IEEE International Symposium on Circuits and Systems, May 2000, pp. 665-668. (ISCAS)(EI)