[H10]	Shih-Nung Wei, Yuandi Surya, Jen-Tsung Yu, and Yi-Ming Wang, “Low-Power Fast-Lock Delay-Recycled Clock Skew-Compensation And/Or Duty-Cycle-Correction Circuit,” 入圍第22屆VLSI Design/CAD最佳論文,Aug. 2011.
[H9]	Jian-Shiun Chen , Yi-Ming Wang, and Yu-Juey Chang, “A 230-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18um CMOS,” 入選第44屆DAC University Booth，並獲頒2007年思源 EDA 獎勵金
[H8]	Jian-Shiun Chen , Yi-Ming Wang, and Yu-Juey Chang, “應用於32位元RISC之單一超低電壓源設計方法,”CIC 晶片製作特別設計獎,2007
[H7]	Yi-Ming Wang, “Circuits for System Clocking,” 教育部 System Level Design (SLD) 聯盟專題演講,Apr. 2007.
[H6]	Jian-Shiun Chen , Yi-Ming Wang, Yu-Juey Chang, Jinn-Shyan Wang, Chingwei Yeh and Tien-Fu Chen, “A 230-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18um CMOS,” DAC/ISSCC Student Design Contest Winner, 2007.
[H5]	Jian-Shiun Chen, Jinn-Shyan Wang, Yi-Ming Wang and Chingwei Yeh, “A 230-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18um CMOS,” ISSCC Silkroad Award Winner, 2007.
[H4]	Yi-Ming Wang, “All-Digital CMOS Phase Alignment and Duty-cycle Adjustment Circuits,” 教育部顧問室混合訊號式積體電路設計聯盟積體電路設計碩士論文觀摩競賽論文演講, Oct. 2005.
[H3]	Yi-Ming Wang, “A low-power half-delay-line direct-skew-compensation circuit, ” 台灣積體電路設計學會沈文仁教授紀念年度論文獎,Aug. 2005.
[H2]	Yi-Ming Wang and Jinn-Shyan Wang, “A low-power half-delay-line direct-skew-compensation circuit,” 教育部矽智產競賽不定題組特優,2003.
[H1]	Yi-Ming Wang and Jinn-Shyan Wang, “A low-power one-delay-line all-digital delay locked loop, IEEE/ACM ISLPED Design Contest Winner, Aug. 2002.